The present invention relates generally to power transistors, and more specifically to metal-oxide-semiconductor-gated (MOS-gated) power transistors with silicon-germanium (SiGe) sources, wells, channels, poly silicon-germanium gates, or a combination thereof.
Trench-gated power MOSFET devices are popular choices for use in several demanding applications, such as DC-to-DC converters. These applications can be very harsh, putting a tremendous strain on these transistors. For example, sourcing and sinking large currents into an inductive load can result in large voltage transients at one or more of the device's terminals. Specifically, a large voltage excursion seen by a trench-gated power MOSFET can activate a parasitic npn transistor, leading to a destructive failure. A less catastrophic, but still performance-degrading event, can occur when a large transient forward-biases a device's body diode, slowing the transistor's reverse recovery.
These inductive effects can limit the efficiency of a DC-to-DC converter, thereby wasting power. Other limits on efficiency include the physical limitations of the trench-gated power MOSFETs themselves. For example, parasitic impedances can cause power dissipation and heating of the devices. Among these parasitic impedances is the series resistance of the gates of the devices. While this series resistance can be mitigated using silicide, the efficacy of this procedure is limited due to the physical structure of these transistors. Channel resistance, or Ron, also limits device performance, thus limiting converter efficiency. Larger devices can reduce Ron, but larger devices are more costly.
Accordingly, what is needed are devices, methods, and processes that provide transistors having improved immunity to the effects of large transient voltages and that provide improved performance by reducing parasitic impedances.